Abstract

Resistance calibration in high‑speed input/output (HSIO) physical layers typically uses dedicated automatic test equipment (ATE) channels to force current and measure voltage at an external reference pin. This traditional approach increases testing overhead and limits the capacity for concurrent multi‑site device testing. This disclosure describes a method and system for performing resistance calibration using an on‑chip current sensor. The sensor’s differential voltage sensing pins are connected to the internal resistance network. A mixed‑signal transconductor converts the detected voltage drop into a current, which is then integrated, sampled, and digitized. Internal resistance is calculated from these measurements using Ohm’s Law, and the results are used to program resistance fuses. This approach reduces the reliance on external reference pins and dedicated ATE channels during the calibration process. Consequently, test costs are reduced and multi‑site testing efficiency is improved by decreasing the required number of physical interface pins.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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