Abstract

Traditional Engineering Change Order (ECO) cell verification may require a full‑chip Electro‑Migration and IR (EMIR) analysis to confirm that newly integrated cells do not induce excessive IR drop failures. For large‑scale integrated circuits, this comprehensive simulation creates significant bottlenecks due to high turnaround times and intensive storage requirements. A machine learning‑based methodology is disclosed to predict dynamic IR drop specifically for ECO instances. A partition‑specific model is trained using data from a preceding stable EMIR execution. Physical and electrical parameters, including resistance, slew, load, and peak current, are extracted for new ECO cells and processed by the trained model to estimate effective IR drop. This approach transitions the signoff process from full‑chip simulation to a focused behavioral prediction. Significant reductions in compute time and disk space usage are achieved, enabling rapid validation and closing of late‑stage design modifications without the overhead of exhaustive global analysis.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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