Abstract
Traditional test methodologies for semiconductor devices typically execute Analog and Memory Built‑In Self‑Test (MBIST) sequences in a standalone, serial fashion. This sequential approach involves separate initialization and execution phases for each test block, which contributes to total tester time. Specifically, standalone sequences for components (e.g., Phase Locked Loops (PLL), Digital to Analog Converters (DAC), memory blocks) run independently through Joint Test Action Group (JTAG) or external interfaces. The disclosed method utilizes a concurrency algorithm based on the IEEE 1687 IJTAG standard and Procedural Description Language (PDL) to interleave these test sequences. Digital and analog initialization phases may be combined, followed by the simultaneous execution of MBIST algorithms, analog stabilization, and data capture cycles. By aligning distinct test targets, the total test time is determined by the duration of the longest individual execution phase rather than the sum of all phases. This concurrent execution may reduce the overall time for joint verification of analog and digital memory blocks on silicon.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Subramanian, Karthikeyan; Chunduri, Kasi; Grover, Achin; Gurumoorthy; and Jayachandra, Suman, "Reducing Test Time through Parallel Execution of Analog and Digital Bist Sequences", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9931