Abstract
Integrated clock gating cells (ICG) on a system-on-a-chip (SoC) can be used to conserve energy by selectively disabling the clock signal to inactive parts of the SoC, minimizing unnecessary switching activity. Clock gating can be controlled by an enable (ICG-E) pin. If the ICG-E pin has high combinational depth, controlling the ICG can become challenging. This disclosure describes test-point insertion (TPI) techniques on the ICG-E pin of a SoC that improve controllability while reducing power consumption without substantially increasing the test-pattern count. Per the techniques, test-point nodes are segregated into ICG-E and non-ICG-E categories. Separate control by JTAG (joint test-action group) data registers (JDR) is assigned to ICG-E test-points. ICG-E test-points are disabled in activity-restricted testing. The described technique of separate JDR control for ICG-E test-points achieves substantial reduction in peak capture power without significantly affecting the pattern count.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Siddhapathak, Krunal, "Voltage-drop (IR)-aware Test Point Insertion", Technical Disclosure Commons, (August 11, 2025)
https://www.tdcommons.org/dpubs_series/8444