Abstract
Read-only memories (ROM) incorporate a scan chain to assist in detecting manufacturing defects. This scan chain can share a single flip-flop across multiple ROM outputs. However, sharing of scan flip-flops across ROM outputs can create a controllability issue for the ROM fan-out logic. Testing ROM fan-out becomes challenging, as a single control element drives four outputs, each with potentially different requirements for fault excitation and detection. This disclosure describes techniques that insert custom test points to improve the controllability and observability of the fan-out and fan-in logic cones of read-only memories (ROMs). By placing test points at the ROM outputs, the infeasibility of inserting test points within the ROM is taken into account, while improving the observability/controllability of the ROM. Control and observe points are implemented using a single test-point flip-flop, such that test coverage is substantially expanded without a significant increase in area.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Siddhapathak, Krunal and Garg, Ankit, "Custom Test Point Insertion for Improved ROM Test Coverage", Technical Disclosure Commons, (August 11, 2025)
https://www.tdcommons.org/dpubs_series/8443