Abstract
This disclosure describes techniques to reduce scan wire length and test cost when performing a scan stitch for complex circuit designs. Per techniques of this disclosure, design compressor-decompressors (Codecs) are utilized for inter-scan and intra-scan partitions to tackle the problem of inter-scan path distance. In a first method, additional embedded deterministic tests (EDTs) and Codecs are inserted into the design and logical scan partitioning is performed to reduce overall scan wire length. In a second method, a logical scan partition mesh is generated for the design without any additional EDTs, based on which DFT partitions are created. These are then connected using intra-scan chains and inter-scan chains to reduce the overall scan wire length. The techniques can be utilized to reduce overall scan wire length, total wire length, the number of vias, combinational area, internal power consumption, test time, test cost, etc. by enabling a higher shift frequency.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Gonugunta, Vevekanenda; S, Rathina Vel; and Patel, Sagar, "Custom Scan Stitch Techniques to Reduce Scan Wire Length and Test Cost", Technical Disclosure Commons, (August 11, 2025)
https://www.tdcommons.org/dpubs_series/8445