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Abstract

Hash tables, which are sets of (key, value) pairs, are versatile data structures that find use wherever a data value has to be retrieved (looked up) against a key. While high-speed lookup functions can be implemented using content-addressable memories (CAM), CAMs are typically expensive in terms of chip area and power consumption. This disclosure describes a scalable, high-performance hardware hash-table design that occupies little area and consumes low power. High speed is achieved by merging the results of multiple hash tables with distinct hashing functions that operate parallelly. The described high-performance hash table is capable of parallel update and lookup operations and can be used in any application where a rapid lookup of data is sought against a key.

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Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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