Abstract
This disclosure describes techniques for verification of a Network-on-Chip (NoC). Per techniques of this disclosure, verification IP (VIP) is designed to include all the blocks of the NoC as a virtualized structure within the VIP. The virtualized NoC is utilized to perform verification tasks associated with the NoC, e.g., to provide stimulus sequences, bus functional models, checkers, coverage models, etc., associated with a particular block in the design. Virtualization of the NoC enables efficient verification of features of the NoC at the block level. During verification, a device under test (DUT) is assigned and connected to a corresponding endpoint. The VIP can be connected to multiple design nodes that can be connected in parallel, thereby speeding up the verification process. Storage is included in the VIP to record the network states and/or relevant signal patterns that can be utilized as test patterns.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Mesh Network Virtualization for Verification of Network-on-Chip (NoC)", Technical Disclosure Commons, (January 30, 2025)
https://www.tdcommons.org/dpubs_series/7784