Abstract
Designing the power delivery network of a system‑on‑chip (SoC) involves repeated changes to the layout and to the power grid, and engineers conventionally re‑evaluate each change with a commercial static current‑resistance (IR) drop analysis. These analyses can run from tens of minutes to several hours across many compute workers, which lengthens each design iteration. This disclosure describes a machine‑learning approach that estimates per‑node static IR drop for multi‑million‑node power grids from electrical and spatial features of a design database. The approach provides two complimentary techniques: a gradient‑boosted decision‑tree regression that predicts incremental IR drop from extracted power and resistance features, and a U‑Net convolutional network that maps effective‑resistance and power‑density images to an IR‑drop heatmap. Together, these techniques shorten iteration turnaround while reserving a full commercial analysis for final signoff.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Pendyala, Prateek, "Machine‑Learning Estimation of Static IR Drop in System‑on‑Chip Power Grids Using Gradient‑Boosted Regression and Image‑to‑Image Translation", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11555