Abstract
During silicon debug, a system-on-chip (SoC) captures its internal sequential state through a scan-based extraction step, referred to as Scandump. Moving the design from functional operation into Scandump mode is an asynchronous event, where a glitch on a reset or clock signal can toggle sequential elements and corrupt the captured state. This document describes a verification method that freezes the design with a global clock-stop signal, writes a known random seed in parallel into the scannable flip-flops (scan flops) as value A, moves the design into Scandump mode, and samples the resulting flop state in parallel as value B. Comparing value A against value B detects corruption, where the bit index of any mismatch points to the affected logic or clock and reset path. The method offers per-flop coverage and quick feedback within a design-verification environment.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Garg, Sunder; Narayanan, Prakash; Siddhapathak, Krunal; Sharma, Shivam; and Parasrampuria, Mayank, "Detecting Scan Flop State Corruption During a Functional-to-Scandump Mode Transition Using Parallel Seed Initialization and Comparison", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11556