Abstract
In the physical design of a system‑on‑chip (SoC) layout, design‑rule‑check (DRC) violations often appear late, during detailed routing (a stage that can take days to complete and that may trigger repeated placement adjustments). This document describes a method that estimates where DRC violation hotspots may gather earlier in the process, working from feature maps that become available after placement and global routing. The method arranges these maps (macro regions, cell and pin densities, rectangular uniform wire density (RUDY) maps, and routing congestion) as multi‑channel two‑dimensional inputs to a fully convolutional network (FCN) built as a multi‑scale encoder‑decoder with skip connections and large convolution kernels. The network returns a heatmap that indicates regions where violations may concentrate. Producing this prediction in seconds, the method can help designers direct placement refinement toward problem regions sooner.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Pendyala, Prateek, "Early Prediction of Design‑Rule‑Check Violation Hotspots from Placement‑Stage Congestion Feature Maps Using a Fully Convolutional Network", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11554