A Place‑and‑Route‑Independent Solver for Early Voltage‑Drop Estimation of System‑on‑Chip Power Grids
Abstract
Designing the power grid of a system‑on‑chip (SoC) balances two competing goals: a denser grid maintains voltage drop within a target, while a sparser grid frees routing resources for timing closure and layout density. Reaching a workable balance calls for repeated passes through grid design, electromigration and voltage‑drop analysis, floor-planning, and place‑and‑route. Preparing those passes with separate commercial tool flows can take up to forty minutes for a single grid specification. This document describes a standalone solver that reads a power‑grid specification, builds a resistor‑and‑via mesh model of the grid, and computes the direct‑current node‑voltage distribution by assembling and solving a sparse conductance matrix. The solver reports voltage‑drop histograms and heatmaps within a few minutes, giving designers an early estimate for comparing grid options before committing to a full physical‑design pass.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Pendyala, Prateek, "A Place‑and‑Route‑Independent Solver for Early Voltage‑Drop Estimation of System‑on‑Chip Power Grids", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11553