Automated Clock Domain Crossing Maximum Delay Constraint Application Using Intermediate Anchor Gates
Abstract
The technology manages clock domain crossing paths by applying a maximum delay constraint to a designated intermediate anchor gate instead of the final destination flip-flop. The register-transfer level configuration instantiates a specific logic gate, such as a MASK AND gate, as this anchor point and assigns it a standardized name. During compilation, a software script automatically discovers these anchors by name and applies a localized, point-to-point delay constraint directly to the pins of the anchors. This pin-to-pin anchoring decouples the timing constraint from the final sampling logic. This approach results in greater placement flexibility for the destination logic across the physical design, even in different physical partitions, and reduces manual effort and false timing violations.
Keywords: clock domain crossing, physical design, timing constraint, pin-to-pin anchoring, MASK AND gate, register-transfer level anchor, maximum delay constraint, high-frequency digital design
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Recommended Citation
N/A and N/A, "Automated Clock Domain Crossing Maximum Delay Constraint Application Using Intermediate Anchor Gates", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11421