Abstract
Conventional semiconductor fault models often assume a linear correlation between fault counts and chip fallout, assigning equal weight to each fault node. This approach fails to account for non‑linear outliers attributed to specific physical design features, leading to suboptimal fallout prediction and inefficient test pattern prioritization. A method is disclosed that utilizes a multi‑layer perceptron network to generate physically aware fault models. A fault feature matrix is constructed from physical design data that incorporates features (e.g., total net length, via density, proximity to power rails). This matrix is processed by a fully connected neural network trained on production fallout data to learn non‑linear weightages for different physical attributes. The model predicts fallout counts for specific test patterns, enabling the re‑ranking of patterns based on their effectiveness. This process may facilitate the removal of low‑contribution patterns, which reduces overall test time while maintaining high design coverage.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Sharma, Sandipan; Vooka, Srinivas; Jalasutram, Maheedhar; and Murthy, Pranav, "Physically‑Aware Fault Modeling and Test Pattern Selection Using Multi‑Layer Perceptron Networks", Technical Disclosure Commons, (April 24, 2026)
https://www.tdcommons.org/dpubs_series/9925