Abstract
The technology described in this paper relates to a hybrid spine-mesh clock distribution network configured to deliver high-frequency clock signals across a network-on-chip fabric in a system-on-chip architecture. The network minimizes clock latency, clock skew, and the overall impact of on-chip variation. The network combines spine-based distribution structures with a grid-like mesh topology. Main spines route the clock signal in a primary direction using upper metal layers while distributed trees or sub-grids branch orthogonally to deliver the clock signal to localized functional areas. A final stage mesh connects to local sequential elements, providing multiple propagation paths that average out localized processing variations.
Keywords: Clock Distribution, Hybrid Spine-Mesh, On-Chip Variation, High-Frequency Clocking, Clock Spines, Clock Grid/Mesh, Network Routing.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Hybrid Mesh-Grid Clock Design for Low Latency and Low On-Chip-Variation", Technical Disclosure Commons, (April 01, 2026)
https://www.tdcommons.org/dpubs_series/9687