Abstract
The technology described in this paper relates to securing high-value machine learning models during inference in various environments, such as edge computing locations. A hardware accelerator, such as an application specific integrated circuit (ASIC), decrypts machine learning model data using internal secrets and memory locking mechanisms. This approach prevents untrusted host systems from reading plaintext data, thereby reducing the trusted compute base (TCB) to the hardware accelerator and its firmware. The implementation of the present technique may include end-to-end encryption to allow for performing a direct key exchange with the hardware accelerator, facilitating private inference without exposing certain data to the host system.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "SECURING MACHINE LEARNING MODELS DURING EDGE INFERENCE", Technical Disclosure Commons, (April 01, 2026)
https://www.tdcommons.org/dpubs_series/9685