Abstract
The technology described in this paper relates to a technique for calculating mean time between failure (MTBF) for a system-on-chip (SoC) based on clock topologies of synchronizers. When a source clock and a destination clock are derived from independent sources, such as separate crystals, the source and destination clocks are truly asynchronous with each other, and their phase relationship drifts randomly over time. In contrast, when the source and destination clocks are labeled as being asynchronous but share a common root source, e.g., a phase-locked loop (PLL) or a clock divider that creates a clock signal from an input clock source, their phase relationship is fixed and deterministic. The technique of this paper switches between probabilistic and deterministic analysis of an MTBF for each synchronizer based on whether the source and destination clocks are truly asynchronous or are based on a common root source. For every synchronizer, the technique computes a specific failure rate based on the appropriate analysis technique for the specific synchronizer. Then, an aggregate of the distinct failure rates can be computed to obtain an MTBF metric for the SoC.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "METHOD AND SYSTEM FOR CALCULATING MEAN TIME BETWEEN FAILURES (MTBF) IN EDGE-LOCKED ASYNCHRONOUS AND FULLY ASYNCHRONOUS CLOCK CROSSINGS", Technical Disclosure Commons, (April 01, 2026)
https://www.tdcommons.org/dpubs_series/9684