Abstract
The present disclosure is directed to generating architecture-aware voltage-frequency (VF) scaling curves for semiconductor designs utilizing logic depth normalization to predict post-silicon performance across diverse process, voltage, and temperature (PVT) corners. An approach involves ingesting raw library characterization data for representative standard cells and converting target frequencies into a normalized metric based on cell-specific propagation delays. By iterating through multiple critical path compositions, the approach can identify a worst-case stage depth that represents the architectural speed limit of the design across all corners. This limiting constraint is then mapped back to the raw delay data across a full voltage spectrum to synthesize a unified VF curve. The approach also captures non-linearities such as stack effects and PVT inversion that traditional ring oscillators and static timing analysis may overlook, thereby ensuring timing closure and optimizing energy efficiency for advanced process nodes.
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Recommended Citation
N/A, "Post-Silicon Performance Prediction", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9644