Abstract
Dynamic voltage drop during scan-shift operations serves as a prominent cause of yield loss in advanced semiconductor nodes. This occurs when large numbers of flip-flops toggle simultaneously, creating a spike in current demand that results in localized voltage droops. These droops lead functional chips to fail manufacturing tests, resulting in false failures. Standard mitigation methods (e.g., reducing clock frequency or applying heuristic gating) provide a means of managing these voltage drops but often increase testing duration or lack a provable mathematical basis.
A spatial optimization framework is disclosed for selecting flip-flops for output gating. The chip floorplan is partitioned into uniform tiles to identify and rank regions with voltage violations. A backward fan-in tracing method is utilized to map these violations to specific source flip-flops. An impact score is calculated for each candidate based on fan-out breadth, violation severity, and toggle rates. A greedy 0-1 knapsack formulation is applied to select an optimal set of flip-flops for gating within a defined resource budget. As a result of the framework, significant improvements in voltage stability are achieved while maintaining testing efficiency.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Gotra, Vishant and Pendyala, Prateek, "Knapsack Based Selection of Scan Flip-Flops for Dynamic Voltage Reduction", Technical Disclosure Commons, (March 05, 2026)
https://www.tdcommons.org/dpubs_series/9451