Abstract
This disclosure describes an automated method for hardware patch generation to update register array values without resynthesis. By comparing new and original RTL designs, the method identifies required changes and maps them to the physical netlist. Flip-flop reset values are modified by inserting inverters at data inputs and outputs instead of changing cell types. This flow utilizes metadata to maintain logical mapping throughout design stages. The resulting approach significantly reduces turnaround time and improves subsystem power-up latency.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
V, Shankar Raj; Kothandaraman, Rajagopalan; and Patel, Ronak Subhas, "Automated Mapping and Patching for Register Arrays", Technical Disclosure Commons, (February 27, 2026)
https://www.tdcommons.org/dpubs_series/9411