Abstract
This disclosure describes a semiconductor architecture designed to eliminate dynamic idle
power consumption in Edge AI applications by utilizing clockless, event-driven logic to execute
linear-complexity State Space Models (SSMs). The system replaces the global synchronous
clock with local handshake protocols (Muller C-elements) implementing Pulsed Static CMOS
logic. This hardware substrate is coupled with a "Metabolic Gating" software router that
dynamically switches between low-precision "reflex" networks and high-precision "reasoning"
networks based on real-time energy availability and input "surprise" (prediction error). The
disclosed invention enables "Zero-Idle" operation, where power consumption scales strictly
linearly with input token arrival, achieving near-zero leakage during inter-token silence.
Creative Commons License
This work is licensed under a Creative Commons Attribution-No Derivative Works 4.0 License.
Recommended Citation
Church, Samuel John, "TECHNICAL DISCLOSURE: Zero-Idle Asynchronous Hardware Architecture for Linear-Complexity State Space Models and Metabolic Gating", Technical Disclosure Commons, (February 06, 2026)
https://www.tdcommons.org/dpubs_series/9284