Abstract
During the testing of integrated circuits (IC), simultaneous switching of instances in a region of the IC increases transient current and causes a voltage drop (also referred to as IR drop). Such voltage drops can interfere with proper testing of the chip and complicate fault detection. This disclosure describes techniques that leverage power-aware analysis to predict the locations of IR hotspots that may arise during ATPG testing of integrated circuits. Compared to traditional structural analysis, the techniques improve the accuracy of prediction of IR hotspots, refine switching activity constraints for ATPG, and generate patterns with realistic power. The techniques produce data that are consistent with the results of functional EMIR sign-off.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Girish, Aditya; Pandey, Praphulla; Vooka, Srinivas; and Gupta, Vaibhav, "Grid Realistic Voltage Drop Patterns for Structural Testing of Integrated Circuits", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9098