Abstract
In VLSI chip design, congestion hotspots that emerge during place-and-route (PnR) pose a hurdle to routability. Poorly routed designs can lead to various issues such as excessive power consumption, signal integrity, timing violations, reliability, etc. This disclosure describes congestion-aware, adaptive techniques for the placement of blockages using gradient-based placement (GP) spirals and radial-diagonal scaling to enhance routability and wire utilization in VLSI design. Per the techniques, blockage placement is continually updated based on real-time routing feedback. The resulting iterative refinement enables a dynamic response to congestion shifts. Initial blockage placement is done using GP spirals and/or radial-diagonal utilization. Global routing is run, and congestion is analyzed to determine the locations and intensities of congestion hotspots. Blockage density is dynamically adjusted to resolve any new congestion that emerges. The procedure is repeated until optimization is complete. The techniques advantageously enable real-time adaptation during PnR, reduce the number of iterations needed for congestion closure, and improve overall routability and timing.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Mudgil, Pankaj; Dayani, Navin; Bargurjar, Vipin; Tyagi, Arun; and Malhotra, Neil, "Adaptive Blockage Placement in VLSI Design for Enhanced Utilization and Congestion Reduction", Technical Disclosure Commons, (July 02, 2025)
https://www.tdcommons.org/dpubs_series/8305