Abstract
During automatic test pattern generation (ATPG) testing of integrated circuits, collateral clock propagation and high switching activity can occur in partitions not being tested, e.g., within the debug-and-system unit. This unintended activity can generate an excessive current draw that can cause excessive heat generation, potential damage to test probes and boards, reduced test safety, etc. This disclosure describes techniques to mitigate excessive current draw within the debug-and-system unit partition of a system-on-chip (SoC) being scan-tested using ATPG by augmenting the SoC with logic that gates and confines the propagation of the clock to blocks of the chip currently being tested. The techniques reduce test-induced current to safe levels, approaching the expected functional current draw, thereby preventing damage to test probes and boards, alleviating safety concerns, and ensuring the reliability of the silicon testing process.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Gonugunta, Vevekanenda; Prajapati, Ajaykumar; Kota, Aditya; Satyanarayan, Nischal; and Gottumukkala, Rajesh, "Protecting Test Equipment from Current Surges due to Non-target Blocks", Technical Disclosure Commons, (July 02, 2025)
https://www.tdcommons.org/dpubs_series/8303