Abstract
A front-end stall in computing occurs when the processor is waiting for instructions to execute. Front-end stalls reduce instruction throughput and thereby negatively impact the performance of the processor. This disclosure describes techniques to improve instruction caching efficiency in processors by identifying instructions that are unlikely to be reused. The techniques can reduce the incidence of front-end stalls, thereby improving instruction throughput and processor performance. Per the techniques, the instruction set architecture (ISA) of the processor is extended with new hint instructions, e.g., a push hint and a pop hint. Instructions between the push hint and the pop hint are marked as less likely to be reused.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Improving Instruction Throughput by Stacking Instruction-caching Hints", Technical Disclosure Commons, (June 19, 2025)
https://www.tdcommons.org/dpubs_series/8252