Abstract
This disclosure describes techniques to thermally characterize three-dimensional integrated circuits (IC). Per the techniques, logic is incorporated into the IC (chip-under-test) that can generate random data, e.g., pseudorandom binary sequence (PRBS), at controllable toggle rates. The random data toggles across the entire die. A power-control mechanism controls the toggle rate in a fine-grained manner. Thermal and voltage sensors integrated into the chip-under-test enable real-time monitoring of temperature and voltage and generate data that can be used to analyze the power consumption, thermal characteristics, and overall health of the chip.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Enhanced Heater for 3D ASIC Chip Design", Technical Disclosure Commons, (June 02, 2025)
https://www.tdcommons.org/dpubs_series/8181