Abstract
This disclosure describes optimized emulation of integrated circuits (ICs) based on migration of information from scan test signal flows (DFT signals). Per techniques of this disclosure, DFT signal flows such as scan mode signals and scan clocks are automatically migrated to emulation signal flows and tied off during emulation such that they are excluded during emulation of the IC. Tie-off of DFT signals can enable faster emulation as well as relieve capacity constraints on the emulation platform. In some implementations, automatic scripts may be utilized to generate emulation code based on the functional tests to be performed and the DFT code base. An indication to perform optimized emulation flow is received. Signals associated with test flow are identified. The identified test flow signals are tied-off automatically and migrated to an emulation code base. Emulation of the IC is performed based on the emulation code base that excludes the DFT logic.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Integrated Circuit Emulation Based on Scan Mode Signal Flow", Technical Disclosure Commons, (December 05, 2024)
https://www.tdcommons.org/dpubs_series/7626