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Abstract

The disclosure describes a single match-processor instruction that forms a direct table index using mask-boundary concatenation of two packed register fields, loads a selected table entry into one of a set of data registers, and dynamically selects the next ALU instruction using an upstream-provided instruction value. The index is created without an adder or multiplier by masking disjoint bit regions of two operands and combining them with a bitwise OR, implementing a logical concatenation at a power-of-two row-length boundary. The index is optionally constrained by a size mask and a 24-bit limit, enabling tables up to 2^24 entries. A sentinel index value (e.g., zero) indicates a miss and triggers a static override instruction, while non-sentinel indices trigger the dynamically selected next instruction. A per-table control block provides base address, size, entry size, and enable fields, and the load address is computed using the base and an index-dependent shift corresponding to entry size.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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