Abstract
The disclosure describes data-plane branching in a match-action pipeline by overriding a next-stage instruction identifier pair stored in a writable pseudo-register. A per-packet-type dispatch table provides, for each stage, an even-slot and odd-slot next-stage MPI-ID pair. A pseudo-register x61 exposes the next-stage MPI-ID pair as writable fields, enabling conditional updates based on lookup status signals for a base-match table (BMT) and a tertiary-match table (TMT). An instruction opcode (CSMPIID) conditionally overwrites either the even half or odd half of x61 based on selected conditions encoded in an immediate field and based on stage lookup status (miss/hit). A priority policy applies across conditions and across table types (miss before hit; BMT before TMT), with mutual exclusion between BMT-driven and TMT-driven overrides per half while allowing the even and odd halves to be independently updated. If no selected condition fires, x61 retains the static dispatch-derived value. A fetch unit reads x61 to select the subsequent stage instruction identifiers, enabling fast-path retargeting such as bypassing policy to an encapsulation-only path on a CT-hit condition.
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Recommended Citation
Anonymous, "Data-Plane Branching via Next-Stage Instruction-ID Override", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/12561