Abstract
A scan test program for a large digital integrated circuit block typically contains thousands of automatic test pattern generation (ATPG) patterns. A test engineer traditionally evaluates a reduction that saves automatic test equipment (ATE) time by a single die‑wide aggregate number that carries no spatial location information. The rest of the die can therefore dilute a total coverage loss in a small region to a few hundredths of a percentage point (pp). To address this deficiency, this disclosure describes a spatially weighted scoring method that resolves each fault to a grid cell and weights each lost fault exponentially by the deficiency of that grid cell. The method aggregates the weighted losses into a spatially weighted loss R that is at least the aggregate loss, allowing a test engineer to test R against an existing coverage‑loss budget. A greedy reduction loop removes candidate pattern subsets (e.g., scenarios, pattern groups, test‑compression channel groups, or individual scan patterns) in order of weighted loss per unit test cost while R stays within the budget. The method can reject a reduction that removes most or all coverage from a few grid cells at a small aggregate loss.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Pandey, Kartikeya; Vooka, Srinivas; and Prajapati, Ajaykumar, "Spatially Aware Test Pattern Optimization", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/12428