Abstract
At-speed delay testing of a system on a chip (SoC) applies two-vector patterns to detect transition delay faults (TDFs), and a launch-on-capture (LOC) test can leave a transition difficult to launch at a node of high combinational depth. A prior multiple scan enable (MSE) hybrid method supplies separate scan enable (SE) signals to launch flip-flops and capture flip-flops, but its coverage varies with how the local SE signals are connected. To address these deficiencies, this disclosure describes a conflict-aware scan enable system that pairs a programmable scan enable controller (PSEC) with a conflict-aware chromatic partitioning (CAP) flow. The PSEC produces a bus of programmable SE outputs from a serially loaded control vector. The CAP flow traces the fan-in cone of each scan flip-flop and assigns a launch flip-flop and the capture flip-flop that it drives to different SE outputs. The system can reduce pattern counts and test time.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Gonugunta, Vevekanenda and Garg, Ankit, "Programmable Scan Enable Control With Conflict-Aware Partitioning of Scan Flip-Flops for At-Speed Delay Testing", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11992