Abstract
A system on a chip (SoC) that merges voltage rails onto fewer buck regulator phases leaves a shared rail with a narrow peak current margin. A synchronized compute burst on the shared rail can drive a current spike that trips over-current protection or collapses the rail voltage before software can respond. To address this limitation, this disclosure describes a power management method that separates voltage control from frequency control inside a subsystem power management block. Under that separation, a software layer retains authority over the rail voltage, and a hardware-aggregated frequency limit clamps a clock frequency of logic powered by the shared rail within ten microseconds of a detected peak current event. Because the rail voltage holds steady during mitigation, the clock frequency recovers without a voltage ramp, and the SoC can merge rails on a reduced buck regulator phase count.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Vijay, Anchal and Mittal, Arpit, "Decoupled Voltage and Frequency Scaling for Low-Latency Peak Current Mitigation on Shared Power Rails", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11990