Abstract
A shared resource on a system on a chip (SoC) holds internal timing parameters that correspond to an operating point supplied to it. Where that point shifts without a matched parameter update, the resource may behave non-deterministically, corrupt stored data, or sustain damage. One conventional safeguard, stalling traffic at an entry boundary of a shared target controller can block the shared fabric and cut a configuration host off from control registers. This publication discloses a method that places request and acknowledge registers in an independent register block on the system fabric interconnect, so handshake signaling stays clear of the operational data path. A secure management host (SMH) stages target parameters in a second configuration bank while the resource keeps running on the first bank. A sideband request then drains work in flight and raises back-pressure behind the address decoder, so the parameter swap and the clock change proceed without deadlock or bus error exceptions.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Sinha, Rohit; Narwaria, Rupendra; Visvesha, Jeevan; Jeemon, Jikku; and Ellur, Harsharaj, "Graceful Operating Point Transitions of Shared System on a Chip Resources Using Staged Configuration Banks and Externalized Handshake Registers", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11977