Abstract
Interconnects in a system on a chip (SoC) often provide virtual channel (VC) separation on request paths but not on response paths, under the assumption that initiator transaction limits keep response contention low. In a heterogeneous device, initiators, targets, and the interconnect may run at differing frequencies and response acceptance bandwidths. Read data can then back up through the interconnect resulting in lower dynamic random-access memory (DRAM) efficiency. A disclosed method addresses this by regulating read request issuance at the target, where initiator traffic is aggregated. The method attributes returning read data to the read VC that requested it, then evaluates the count for each VC against a watermark register indexed by VC and by urgency level. A count above that watermark prevents read requests for that VC from being issued to the memory controller. Issuance resumes as the count falls, aligning the request rate with the achievable response rate.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Totte, Rob, "Response Path Occupancy Watermarks for Throttling Per-Virtual-Channel Read Requests at the Memory Controller of a System on a Chip", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11976