Abstract
A vertical power (VPWR) module architecture delivers electrical power to three-dimensional stacked semiconductor chiplets (such as TPU, GPU, xPU) packages using distributed sub-phase building blocks. The architecture divides the phases of a multi-phase power stage, and the voltage outputs those phases feed, into two or more independent power rails, so that a four-phase stage yields two, three, or four independent voltage outputs. These sub-phase units physically map onto interleaved power rails across a ball grid array (BGA) footprint of the semiconductor packages. Positioning the sub-phase units directly beneath corresponding power rail contact locations shortens current travel paths through printed circuit board (PCB) layers. This spatial alignment suppresses lateral current flow and reduces power delivery network (PDN) conduction losses. The reduced electrical dissipation lowers thermal stress on the PCB and improves power delivery performance across computing hardware.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Distributed Vertical Power Module Building Blocks for Interleaved Power Delivery to Three-Dimensional Stacked Chiplets", Technical Disclosure Commons, (September 16, 2026)
https://www.tdcommons.org/dpubs_series/11753