Abstract
A hierarchical port scheduler for a multi-engine network interface controller provides unified transmit arbitration across independent protocol engines sharing traffic classes and downstream resources. The scheduler ingests transmit descriptors, optionally computes full on-wire frame length, and stores descriptors in per-port queues. A two-level hierarchical token bucket applies per-queue and per-group committed/peak rate limiting with configurable queue-to-group mapping. Per-queue and per-group colors are combined via a programmable truth table to form a combined color, and a global strict color priority selects eligibility vectors across groups. An eligibility masking stage accounts for downstream constraints including transmit buffer credits, priority-based flow control pause, dispatch interlock, and host memory interface flow control. Per-group DWRR arbitration, strict priority merging, optional per-port rate limiting, and cross-port round-robin select a winner. Token/deficit updates may be deferred until acceptance to avoid credit leakage under speculative overspeed. Dual instances may operate at host memory fetch and transmit buffer egress.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Anonymous, "Hierarchical Traffic Scheduling Architecture for Multi-Engine Network Interface Controllers", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11577