Abstract
This technology integrates Event-Triggered Selective Rank Warming and an Always-On Shadow Completion Bridge to manage power-gated Compute Express Link Dynamic-Capacity Memory. A memory controller intercepts a mandatory out-of-band memory allocation handshake and uses this event to deterministically trigger a power-exit sequence for only the specific physical memory blocks being allocated. If a host access occurs before this sequence completes, the Always-On Shadow Completion Bridge handles the request using an always-powered internal staging store. The bridge emulates read completions with deterministic data and absorbs write transactions, preventing host timeouts. After the physical memory becomes fully operational, the controller transparently drains the absorbed writes from the internal staging store to the physical media. This architecture hides the Physical Wake Latency from the host central processing unit (CPU), eliminating the risk of Machine-Check Exception (MCE) crashes. The approach preserves the energy savings of power-gating and complies with the CXL.mem protocol, requiring no host software or hardware modifications.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Girish, Vadlamudi Venkata, "Event-Triggered Selective Rank Warming and Always-On Shadow Completion for Compute Express Link Dynamic-Capacity Memory", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11571