Abstract
A subsystem for network packet processing uses a pool of shared, configurable processing resources. The architecture includes these shared processing elements, a centralized event processing engine, and a partitionable shared memory. The event processing engine accumulates events from the packet pipeline and forwards them as tasks to the processing elements. These elements, which may be implemented as microcode sequencers, execute writable microcode firmware to perform logical and arithmetic operations and handle interrupts independently of a central processing unit. The processing elements access the shared memory to exchange state and packet data between processing stages. This approach improves resource utilization and allows packet processing rules to be modified via firmware, resulting in a reduction in integrated circuit die size, power consumption, and thermal output.
Keywords: packet pipeline, shared memory, event processing engine, shared processing element, microcode sequencer, execution element
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A and N/A, "Resource-Constrained Multiprocessing Packet Pipeline with Shared Configurable Elements", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11423