Abstract
The technology described in this paper relates to a packaging structure and associated methods for reducing out-of-plane deformation. The structure introduces a stiffening element bonded to the bottom side of a package substrate to counteract the coefficient of thermal expansion of semiconductor chips positioned on the top side of the substrate. This arrangement creates a highly symmetrical structure that effectively minimizes warpage without consuming valuable top-side surface area. The bottom-mounted element may feature various openings to accommodate solder balls and other electrical components. By reducing overall package warpage, the structure facilitates the use of finer pitch connections and enhances overall computing performance capabilities.
Keywords: package warpage, bottom stiffener, coefficient of thermal expansion, semiconductor packaging, microelectronics.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A and , "Stiffeners for Package Warpage Control", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11382