Abstract
Distributed reconfigurable logic cells are integrated across a system-on-chip and/or multi-chiplet package to enable post-tapeout remediation of defects in hardened circuitry without redesign. Small micro-FPGA cells are placed proximate to selected hardened IP blocks and coupled via local interfaces and steering circuitry. After fabrication, a configuration controller programs one or more proximate cells at boot time and/or runtime with remedial logic that replaces, augments, or bypasses defective behavior, and activates routing/steering to apply the fix. Unused cells may be power-gated or clock-gated to reduce static and dynamic power. The cells may also be repurposed for debug, test, monitoring, security patches, protocol adaptation, or feature updates.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Anonymous, "Distributed Reconfigurable Logic Cells for Zero-Respin Post-Tapeout Silicon Defect Recovery", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10614