Abstract
The technology described in this paper relates to a method for optimizing the compilation flow of field-programmable gate arrays by streamlining memory resource allocation. The approach uses pre-partitioned memory wrappers during the register transfer level design phase to bypass automated memory mapping. By decomposing large design memories into sub-memory blocks that correspond directly to native physical memory dimensions, the method reduces computational overhead and shortens verification cycles. Two distinct allocation strategies—depth-first and width-first—are evaluated to optimize hardware resource utilization. Keywords: field-programmable gate array, emulation, compilation, memory mapping, register transfer level, wrappers, and resource allocation.
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Recommended Citation
N/A and , "Method for Accelerating Field-Programmable Gate Array Emulation Using Pre-Optimized Memory Implementation", Technical Disclosure Commons, (June 29, 2026)
https://www.tdcommons.org/dpubs_series/10598