Abstract
System‑on‑chip architectures often employ primary power controllers to direct the operational states of various internal sub‑systems. Problems can arise during periods of sub‑system inactivity, as the primary power controller remains active to monitor the sleeping domains, resulting in continuous power consumption. The disclosed technology utilizes a secondary power controller manager to govern the clocking and power states of the primary power controller. By evaluating hardware handshakes, initiating duration counters, and deploying finite state machines, the power controller manager transitions the primary power controller into a clock‑gated or power‑gated state during extended periods of sub‑system inactivity. In this way, the disclosed technology reduces the baseline energy draw of the overall integrated circuit.
Creative Commons License
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Recommended Citation
Prasad, Janardan, "Regulating Operational States of an On‑Chip Power Controller", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10572