Abstract
Test engineers utilize at‑speed transition delay fault testing to maintain product quality in sub‑nanometer semiconductor designs. The standard launch‑on‑capture (LOC) methodology may face controllability limitations due to functional logic dependencies. These dependencies may prevent the testing system from activating targeted transitions, which might lead to test escapes. While alternative methods (e.g., launch‑on‑shift (LOS), control test points) exist, these alternative methods may introduce timing closure challenges or performance degradation in high‑frequency circuits. This disclosure describes a hybrid methodology utilizing localized multi‑scan enable (MSE) generator logic. A testing system temporarily enables a localized shift mode on specific launch flip‑flops to transform sequential fault sites into combinational fault sites. This hybrid methodology allows a testing system to force targeted transitions through scan‑in ports while the destination flip‑flops maintain functional capture. Consequently, the testing system achieves high at‑speed test coverage without adding logic to functional data paths or imposing at‑speed timing constraints on global scan enable networks.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Gonugunta, Vevekanenda; Garg, Ankit; Kakkatt, Vipin; and Acharya, Aravinda, "Multi‑Scan Enable (MSE) Hybrid Methodology for At‑Speed Transition Delay Fault Testing", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10570