Abstract
Embedded system implementations of many multimedia and network processing applications are characterized by high performance and low power requirements. The development platform must satisfy tight time-to-market and ease of future upgrade requirements, leading to the advent of programmable multiprocessor system-on-chip (MPSoC) architectures. This paper presents system-level and micro-architectural power optimization techniques mapped to an MPSoC architecture alongside a low-power Network-on-Chip (NoC). By integrating pipelined scheduling, unrolling, Dynamic Voltage Scaling (DVS), and Dynamic Power Management (DPM), alongside hardware-level NoC optimizations, the network power dissipation is reduced by 38%, and system-level power reductions of up to 42% are achieved.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Tummala, Gopi K. and Yalamarthy, Devi, "System and Micro-Architecture Level Methods to Optimize Power in a Multiprocessor System-on-Chip", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10389