Abstract

In this paper, we present an advanced power-management architecture for Vision Conservation Cores (C-Cores)—application-specific hardware coprocessors designed to aggressively reduce energy consumption in compute-intensive signal processing tasks. Synthesized targeting a 45nm process at a 0.9V supply, our design accelerates standard vision kernels—specifically noise, horizontal edge, and vertical edge filters—generated via the Arsenal C-to-Silicon toolchain.

To push the boundaries of extreme energy efficiency, we applied a multi-layered suite of dynamic and design-time power management techniques. At the micro-architecture and physical levels, we implemented multi-stage clock gating, high threshold voltage (HVT) cell modulation to combat dominant leakage currents, and instance-based power-aware placement. Furthermore, we introduce a novel load-time hardware "patching" methodology that fuses multiple independent vision kernels into a single, unified C-Core. This unification approach effectively creates dynamic power islands and allows for a significant reduction in the scan-chain shift register overhead utilized for host-to-core interfacing.

Evaluated using rigorous Energy-Delay Product (EDP) and Energy-Delay-Area (EDA) metrics, our architecture demonstrates profound efficiency gains. While baseline C-Cores already provide up to a 16x energy reduction over host CPU execution, our targeted power management techniques—led primarily by highly effective clock gating—yield an additional 7x (~80%) power savings on top of the 16x baseline. Our silicon-level findings underscore the necessity of balancing power, delay, and area trade-offs, proving that unified, "patchable" C-Core architectures can successfully drive maximum power savings in heterogeneous tile processors.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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