Abstract
This publication describes a hardware architecture for floating-point dot-product arrays that performs exponent alignment using a comparator-free OR-bucketing topology. The architecture uses spatial unrolling to create a single-cycle, parallel-prefix logic tree that is purely combinational. The design exploits algebraic properties to cancel out exponent biases during alignment, which allows the primary timing path to remain completely unsigned and free of bias subtractors. By managing excess timing slack, the system supports various operating modes for artificial intelligence accelerators, including high-throughput and high-efficiency modes. Keywords: floating-point, dot-product array, exponent alignment, OR-bucketing, spatial unrolling, bias cancellation, parallel-prefix logic, artificial intelligence accelerator.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A and N/A, "A Comparator-Free Architecture for Maximum Product-Exponent Detection via OR-Bucketing", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10347