Abstract
This disclosure describes a multi-material semiconductor die designed to mitigate package warpage by adjusting the overall coefficient of thermal expansion of the die structure. By incorporating a secondary material with a higher thermal expansion coefficient than silicon, such as copper, the thermal expansion of the die is increased to more closely match the expansion characteristics of a package substrate. This is achieved through a layered configuration where the secondary material is deposited as a subsection of the die or sandwiched between silicon layers. This approach provides a flexible method for tuning the thermo-mechanical characteristic of the die to improve manufacturing yields and device reliability across various high-performance applications.
Keywords: semiconductor die, coefficient of thermal expansion, copper, silicon, package warpage, multi-material die, thermal expansion mismatch, electroplating, layered die configuration.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Multi-Material Die/Chip to Reduce Package Warpage by Reducing Die to Substrate CTE Mismatch", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10124