Abstract
A framework providing a dual-metric topology assessment evaluates hold-timing vulnerabilities on paths experiencing high divergence and associated voltage drop gradients. The framework utilizes loop delay tolerance and differential drop tolerance metrics to identify fragile paths and apply proactive verification early in the physical design cycle.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Picozzi, Google Case Managers and Pendyala, Prateek, "Framework for Robustness Against Divergent Voltage Drops and High Clock Divergence", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9984
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