Abstract
The disclosed technology introduces an artificial intelligence-based spatial partitioning framework for integrated circuit testing. By extracting physical and electrical features from design instances, the system constructs optimized virtual tiles to manage power constraints dynamically during structural testing. The methodology utilizes machine learning refinement techniques to maintain load balancing and spatial contiguity, allowing test pattern generation tools to operate with granular, region-specific power awareness that aligns with the underlying power distribution network.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Picozzi, Google Case Managers; Parasrampuria, Mayank; and Gotra, Vishant, "Virtual Power-Aware Spatial Tiling Framework for Automatic Test Pattern Generation", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9982