Abstract
The present disclosure is directed to a mechanism for hardware-accelerated fabric convergence via direct remote memory updates in high-performance network fabrics. A publisher switch, upon detecting a local port event such as a link failure or signal degradation, may automatically generate a direct update packet without software intervention. This packet may contain a specific hardware write instruction, a target memory address corresponding to an application-specific integrated circuit (ASIC) memory location of a subscriber switch, and a data payload to modify forwarding state. Upon receipt, the subscriber switch may utilize a dedicated hardware-based direct update parser to intercept the packet, bypass the central processing unit (CPU) and operating system software stack, and execute a direct hardware write to its internal memory, such as an equal-cost multi-path (ECMP) table. By shifting control to the publisher side and automating the update process in fixed hardware logic, the system achieves deterministic, sub-millisecond fabric convergence, significantly reducing packet loss and latency compared to traditional software-centric control plane protocols.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Low-Latency Fabric Convergence via Direct Remote Memory Update", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9600